There are several views under which an integrated electronic circuit can be described, such as a logic view, a schematic view, and a layout view. The view that is closest to the actual fabricated circuit is the layout view where the geometric shapes of all the devices and the wiring connecting them are spelled out. A crucial step in the computer-aided design of an integrated circuit is to verify that the geometric shapes do indeed have the electrical parameter values that were intended in the design. This crucial step is called extraction, and it typically involves the handling of several millions of geometric shapes and their mapping onto electrical circuit parameters such as capacitance, resistance or inductance. The value of an electrical parameter is dependent on the values of the geometric, physical, and manufacturing process parameters. The said dependence is governed by the laws of physics, such as Maxwell's equations. The sensitivities of the electrical parameters are hereafter referred to as the dependent parameters while the geometric, physical, and process parameters will be called the independent parameters. The sensitivity of a dependent parameter with respect to an independent parameter measures the ratio of a change in an independent parameter to a very small and even an infinitesimal change of a given independent parameter with all other independent parameters remaining unchanged.
In computer operated extraction programs, the huge input data volume of the millions of geometric shapes is usually handled using pattern matching with fundamental geometric templates whose nominal values for various parameters of the electrical properties are pre-computed and pre-stored in look-up tables. These lookup tables are keyed to the values of the geometric parameters of a given shape such as the layer of the integrated circuit on which the shape resides, its immediate environment, and its dimensions. Available extraction programs include Assura-RCX (Cadence®), Star-RCXT (Synopsis®), and Erie and 3DX (IBM®). The pre-computed and pre-sorted table of templates is typically generated using nominal values for the electrical parameters.
It is well-known to those skilled in the art that the nominal values of the parameters of the electrical properties of the templates are not sufficient to electrically characterize the design. This is because during fabrication of the circuit the geometric shapes are going to be perturbed with respect to their nominal dimensions. This perturbation is mainly due to the deterministic and statistical variations in the process and design parameters of the manufacturing process and can be thought of in terms of tolerances relative to the nominal values.
One way to deal with variation caused by the perturbations is to generate several look-up tables for each of the fundamental geometric templates. Using this approach, each of the look up tables corresponds to one “corner” in the process and design parameter space. This approach is however no longer really viable in cutting edge IC fabrication due to the very large number of corners that exist in a complex integrated circuit. The number of such corners is being driven up due to the increase in complexity of the semiconductor design and the fabrication process. Therefore, this results in the increase in the number of parameters that have to be taken into account using the corner analysis technique.
Another approach can be used when the process and design parameters have small perturbations around their nominal values. In such a case it is known to use the mathematical partial derivatives (also known as sensitivities) of the nominal values of the design and process parameters as a shortcut to doing corner analysis. It has been found that when the perturbation is small, the corner values (sensitivities) can be obtained from the nominal ones using simple linear extrapolations. In the publication by Labun, A., “Rapid Method to Account for Process Variation in Full-Chip Capacitance Extraction,” IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS SYSTEMS, Vol. 23, No. 6, June 2004, p. 941-951, the problem of calculating the sensitivities, that is, the change in the nominal values caused by the perturbations, of layout shape capacitances with respect to the parametric variations is considered. But the solution provided in this publication relies on the fact that the capacitance parameters of the fundamental templates are given by analytical formulas that are straight forward to differentiate in order to compute sensitivities. This approach is not suitable to the case of a large number of process and design parameters because such analytical formulas are very difficult to obtain. Furthermore, even when such a formula exists, it is not going to be accurate enough across the full ranges of the many parameters involved in the design of a modern day complex integrated circuit.
Chang, N. et al., “Method and System for Determining Statistically Based Worst -Case On -Chip Interconnect Delay and Crosstalk,” U.S. Pat. No. 6,018,623, issued Jan. 25, 2000 uses sensitivities of the parameters of capacitance and resistance electrical properties to produce statistical models for integrated circuit performances when there are statistical variations in the process and design parameters. But Chang, et al do not teach how to compute the sensitivities of the parameters.
U.S. Patent Publication No.: US 2007/0124707 A1, May 31, 2007 of Sutjahjo, et. al., “Method and Apparatus for Facilitating Variation-Aware Parasitic Extraction”proposes a method for computing sensitivities. It addresses the same problem as the one addressed in the present invention, namely, how to augment the look-up table containing the nominal values of parameters of an electrical property as given in the fundamental templates with sensitivity information. One of the advantages of the method Sutjahjo, et al is that it reduces the calculation of sensitivities to that of solving a linear system of equations similar to the one used to compute the nominal values. However it is restricted to special kinds of linear systems, namely, those for which an upper-lower (LU) factorization is available.
Accordingly, a need exists to be able to efficiently determine the sensitivities of the various parameters of electrical properties of complex integrated circuits and whose solution involving a linear system does not suffer the above described restrictions of Sutjahjo, et al.